// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.


// Generated by Quartus II 64-Bit Version 13.0 (Build Build 232 06/12/2013)
// Created on Wed May 25 11:16:52 2016

NiosII NiosII_inst
(
	.clk_clk(clk_clk_sig) ,	// input  clk_clk_sig
	.reset_reset_n(reset_reset_n_sig) ,	// input  reset_reset_n_sig
	.sdram_wire_addr(sdram_wire_addr_sig) ,	// output [11:0] sdram_wire_addr_sig
	.sdram_wire_ba(sdram_wire_ba_sig) ,	// output [1:0] sdram_wire_ba_sig
	.sdram_wire_cas_n(sdram_wire_cas_n_sig) ,	// output  sdram_wire_cas_n_sig
	.sdram_wire_cke(sdram_wire_cke_sig) ,	// output  sdram_wire_cke_sig
	.sdram_wire_cs_n(sdram_wire_cs_n_sig) ,	// output  sdram_wire_cs_n_sig
	.sdram_wire_dq(sdram_wire_dq_sig) ,	// inout [15:0] sdram_wire_dq_sig
	.sdram_wire_dqm(sdram_wire_dqm_sig) ,	// output [1:0] sdram_wire_dqm_sig
	.sdram_wire_ras_n(sdram_wire_ras_n_sig) ,	// output  sdram_wire_ras_n_sig
	.sdram_wire_we_n(sdram_wire_we_n_sig) ,	// output  sdram_wire_we_n_sig
	.epcs_dclk(epcs_dclk_sig) ,	// output  epcs_dclk_sig
	.epcs_sce(epcs_sce_sig) ,	// output  epcs_sce_sig
	.epcs_sdo(epcs_sdo_sig) ,	// output  epcs_sdo_sig
	.epcs_data0(epcs_data0_sig) ,	// input  epcs_data0_sig
	.bus_wr_n(bus_wr_n_sig) ,	// output  bus_wr_n_sig
	.bus_rd_n(bus_rd_n_sig) ,	// output  bus_rd_n_sig
	.bus_addr(bus_addr_sig) ,	// output [15:0] bus_addr_sig
	.bus_data_out(bus_data_out_sig) ,	// output [31:0] bus_data_out_sig
	.bus_data_in(bus_data_in_sig) ,	// input [31:0] bus_data_in_sig
	.key4x4irq_export(key4x4irq_export_sig) ,	// input  key4x4irq_export_sig
	.key4x4_KEY_H(key4x4_KEY_H_sig) ,	// inout [3:0] key4x4_KEY_H_sig
	.key4x4_KEY_L(key4x4_KEY_L_sig) ,	// inout [3:0] key4x4_KEY_L_sig
	.key4x4_irq(key4x4_irq_sig) ,	// output  key4x4_irq_sig
	.lcdspi_MISO(lcdspi_MISO_sig) ,	// input  lcdspi_MISO_sig
	.lcdspi_MOSI(lcdspi_MOSI_sig) ,	// output  lcdspi_MOSI_sig
	.lcdspi_SCLK(lcdspi_SCLK_sig) ,	// output  lcdspi_SCLK_sig
	.lcdspi_SS_n(lcdspi_SS_n_sig) ,	// output  lcdspi_SS_n_sig
	.lcdrs_export(lcdrs_export_sig) ,	// output  lcdrs_export_sig
	.lcdrst_export(lcdrst_export_sig) ,	// output  lcdrst_export_sig
	.lcdleda_export(lcdleda_export_sig) ,	// output  lcdleda_export_sig
	.flag1_export(flag1_export_sig) ,	// output [3:0] flag1_export_sig
	.date_k_export(date_k_export_sig) ,	// output [31:0] date_k_export_sig
	.am_date_k_export(am_date_k_export_sig) ,	// output [31:0] am_date_k_export_sig
	.k_export(k_export_sig) ,	// output [13:0] k_export_sig
	.b_export(b_export_sig) ,	// output [13:0] b_export_sig
	.fm_fate_k_export(fm_fate_k_export_sig) ,	// output [31:0] fm_fate_k_export_sig
	.shift_export(shift_export_sig) 	// output [3:0] shift_export_sig
);

